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Micrologic Design Automation
Distance: 0.4 Mi2033 Gateway Pl Ste 500
95110-3712 San Jose -
Western Technology Investment
Distance: 0.5 Mi2010 N 1st St Ste 310
95131 San Jose -
PLD Applications Inc
Distance: 1.2 Mi2570 N 1st St
95131-1015 San Jose -
Telenet Semiconductor 2000
Distance: 1.0 MiBldg 1701 Junction Ct Ste 200
95112 San Jose -
Scientific Coating Laboratory
Distance: 1.0 Mi350 Martin Avenue
95050 Santa Clara
Website Links
Description
Arteris provides SoC interconnect IP and tools based on its Network-on-Chip (NoC) architecture. The Arteris Network-on-Chip (NoC) architecture borrowed the applicable concepts from the computer networking arena and adapted them to IC design constraints. This solution ensures a balanced tradeoff between performance, silicon area, and power, and reflects an in-depth understanding and integration of the constraints imposed by SoC implementations and semiconductor processes.