-
Keker & Van Nest
Distance: 3.1 Mi710 Sansome St
94111 San Francisco -
Integrated Circuit Support Inc
Distance: 19.3 Mi1001 Center Street
94070 San Carlos -
Digitalvar, Inc
Distance: 17.7 Mi26212 Industrial Blvd
94545-2922 Hayward -
Abeam Technologies
Distance: 18.7 Mi5286 Dunnigan Ct
94546 Castro Valley -
Spectel Research Corp
Distance: 27.0 Mi807 Rorke Way
94303-4410 Palo Alto
Description
Dr. Dadi Gudmundsson has researched and worked in semiconductor yield management for the past eleven years. His primary focus has been the field of semiconductor inspection capacity planning. In this new field his experience includes algorithm research, software development, and consulting service deployment. Other related experience includes test structure based yield learning systems and defect detection algorithms for scanning electron microscopes. Dr. Gudmundsson received a Ph.D. in Industrial Engineering and Operations Research from Berkeley in 2005. His research interests are stochastic and simulation models of production systems. His thesis focused on inspection and metrology capacity planning in semiconductor manufacturing. From 1998-2004 he worked as an inspection planning specialist and consultant at KLA-Tencor. Main responsibilities were the development and deployment of inspection capacity planning tools. He has supervised and personally performed numerous inspection planning projects at leading semiconductor fabs worldwide. Dr. Gudmundsson has published extensively on the topics of inspection and metrology planning [ ]. He has served as a reviewer for IEEEs ICRA conference and currently reviews for IEEE Transactions on Automation Science and Engineering. Dr. Kan Wu worked in semiconductor manufacturing for nine years before attending Georgia Tech for his Ph.D. degree. He received a B.S. degree in nuclear engineering from National Tsinghua University, Taiwan. He received a M.S. degree in Industrial Engineering and Operations Research, a M.E. degree in nuclear engineering from the University of California, Berkeley, and a Ph.D. degree in Industrial and Systems Engineering from Georgia Tech. He has been a senior engineer with Tefen, Limited, and Taiwan Semiconductor Manufacturing Company. In 2003, he joined Inotera Memories Incorporated as an IE manager. His position at Inotera included the master schedule control for constructing a new 10 billion 300mm fab, productivity improvement, layout design and simulations. Dr. Wu holds six US patents, and is a reviewer for several international journals. His current research focuses on quantifying and optimizing the performance of manufacturing systems.